Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / fcvt_d_l.h

diff --git a/riscv/insns/fcvt_d_l.h b/riscv/insns/fcvt_d_l.h
index 68c04827a3704c45deea1bb47e9fee49aca62661..08716cffe2d6af6f3f6844381c84b56c40e8d4fe 100644 (file)
--- a/riscv/insns/fcvt_d_l.h
+++ b/riscv/insns/fcvt_d_l.h
@@ -1,5 +1,6 @@
-require_xpr64;
+require_extension('D');
+require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-FRD = i64_to_f64(RS1);
+WRITE_FRD(i64_to_f64(RS1));
 set_fp_exceptions;