WIP on priv spec v1.9

[riscv-isa-sim.git] / riscv / insns / fcvt_d_wu.h

diff --git a/riscv/insns/fcvt_d_wu.h b/riscv/insns/fcvt_d_wu.h
index 4c562481e200f869f06e6c5aeaf4848331f7ed0b..af893b32dd75352bf94c4106bfca23dcdd7c9da6 100644 (file)
--- a/riscv/insns/fcvt_d_wu.h
+++ b/riscv/insns/fcvt_d_wu.h
@@ -1,4 +1,5 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f64((uint32_t)RS1));
+WRITE_FRD(ui32_to_f64((uint32_t)RS1).v);
 set_fp_exceptions;