Update README
[riscv-isa-sim.git] / riscv / insns / fcvt_l_d.h
index bf03b714b1883671458919bf7252edd6c88a0739..c09e6c4474209623415d398d9f96a0d6e17b1a05 100644 (file)
@@ -1,5 +1,6 @@
-require_xpr64;
+require_extension('D');
+require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f64_to_i64(FRS1, RM, true));
+WRITE_RD(f64_to_i64(f64(FRS1), RM, true));
 set_fp_exceptions;