Implement Q extension

[riscv-isa-sim.git] / riscv / insns / fcvt_l_q.h

diff --git a/riscv/insns/fcvt_l_q.h b/riscv/insns/fcvt_l_q.h
new file mode 100644 (file)
index 0000000..b28bca2
--- /dev/null
+++ b/riscv/insns/fcvt_l_q.h
@@ -0,0 +1,6 @@
+require_extension('Q');
+require_rv64;
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_RD(f128_to_i64(f128(FRS1), RM, true));
+set_fp_exceptions;