WIP. Doesn't work.

[riscv-isa-sim.git] / riscv / insns / fcvt_lu_d.h

diff --git a/riscv/insns/fcvt_lu_d.h b/riscv/insns/fcvt_lu_d.h
index 7be12ed266f207f86e8fe446ba4819d3e8c5a204..3a021204c21278a8b6e17c1a73afa564115e4ad4 100644 (file)
--- a/riscv/insns/fcvt_lu_d.h
+++ b/riscv/insns/fcvt_lu_d.h
@@ -1,5 +1,6 @@
+require_extension('D');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f64_to_ui64(FRS1, RM, true));
+WRITE_RD(f64_to_ui64(f64(FRS1), RM, true));
 set_fp_exceptions;