Implement Q extension

[riscv-isa-sim.git] / riscv / insns / fcvt_q_s.h

diff --git a/riscv/insns/fcvt_q_s.h b/riscv/insns/fcvt_q_s.h
new file mode 100644 (file)
index 0000000..79e6bb6
--- /dev/null
+++ b/riscv/insns/fcvt_q_s.h
@@ -0,0 +1,5 @@
+require_extension('Q');
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f32_to_f128(f32(FRS1)));
+set_fp_exceptions;