Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fdiv_d.h

diff --git a/riscv/insns/fdiv_d.h b/riscv/insns/fdiv_d.h
index aa00c98dcae8ae2e77c30f0e3ed933fa52619c1e..ae7911ae9ae57b314fd1bca5daba43f4af231331 100644 (file)
--- a/riscv/insns/fdiv_d.h
+++ b/riscv/insns/fdiv_d.h
@@ -1,4 +1,5 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_div(FRS1, FRS2);
+WRITE_FRD(f64_div(f64(FRS1), f64(FRS2)));
 set_fp_exceptions;