Use simpler MTVEC scheme

[riscv-isa-sim.git] / riscv / insns / flt_d.h

diff --git a/riscv/insns/flt_d.h b/riscv/insns/flt_d.h
index 01d135a93de845723f52517502feea8c98613aba..7176a961d44f968b34387e68dc95e212f61335b7 100644 (file)
--- a/riscv/insns/flt_d.h
+++ b/riscv/insns/flt_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
-RD = f64_lt(FRS1, FRS2);
+WRITE_RD(f64_lt(f64(FRS1), f64(FRS2)));
 set_fp_exceptions;