Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / flt_s.h

diff --git a/riscv/insns/flt_s.h b/riscv/insns/flt_s.h
index 52eee5d34600f7ac8efca0f2bd974801fa526b27..40acc34b9cefd3a8bfc9c7cdab9ffaa3641ccc43 100644 (file)
--- a/riscv/insns/flt_s.h
+++ b/riscv/insns/flt_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
-RD = f32_lt(FRS1, FRS2);
+WRITE_RD(f32_lt(f32(FRS1), f32(FRS2)));
 set_fp_exceptions;