Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fmsub_s.h

diff --git a/riscv/insns/fmsub_s.h b/riscv/insns/fmsub_s.h
index c6aa418521cdc9952538c5774201f9a733506c37..d46c887e7c746137aebe24e64880fadb3fa34fdb 100644 (file)
--- a/riscv/insns/fmsub_s.h
+++ b/riscv/insns/fmsub_s.h
@@ -1,4 +1,5 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN));
+WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN)));
 set_fp_exceptions;