Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / fmv_x_d.h

diff --git a/riscv/insns/fmv_x_d.h b/riscv/insns/fmv_x_d.h
index da8e72a82ecd0d04eac3e9ab40e9860dcff23872..e1a23f482735b1dd97221b0f69eeaa2bcc98e39a 100644 (file)
--- a/riscv/insns/fmv_x_d.h
+++ b/riscv/insns/fmv_x_d.h
@@ -1,4 +1,4 @@
 require_extension('D');
 require_rv64;
 require_fp;
-WRITE_RD(FRS1.v);
+WRITE_RD(FRS1.v[0]);