Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / fsgnjx_d.h

diff --git a/riscv/insns/fsgnjx_d.h b/riscv/insns/fsgnjx_d.h
index 2bcef6f306a84573a5d4e81ea8e69483da89ad2c..c12173719b79c51d84d4a7fc9a0db5effa4aebd1 100644 (file)
--- a/riscv/insns/fsgnjx_d.h
+++ b/riscv/insns/fsgnjx_d.h
@@ -1,2 +1,3 @@
+require_extension('D');
 require_fp;
-WRITE_FRD(FRS1 ^ (FRS2 & INT64_MIN));
+WRITE_FRD(fsgnj64(FRS1, FRS2, false, true));