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Fix implementation of FMIN/FMAX NaN case
[riscv-isa-sim.git]
/
riscv
/
insns
/
fsub_d.h
diff --git
a/riscv/insns/fsub_d.h
b/riscv/insns/fsub_d.h
index e25eebbdc281b86f4d5aad2974dfcee16be4789a..1418a063d6ebc1a2925e0884e1faf3c94167f92d 100644
(file)
--- a/
riscv/insns/fsub_d.h
+++ b/
riscv/insns/fsub_d.h
@@
-1,4
+1,5
@@
+require_extension('D');
require_fp;
softfloat_roundingMode = RM;
-
FRD = f64_sub(FRS1, FRS2
);
+
WRITE_FRD(f64_sub(f64(FRS1), f64(FRS2))
);
set_fp_exceptions;