WIP. Doesn't work.

[riscv-isa-sim.git] / riscv / insns / fsub_d.h

diff --git a/riscv/insns/fsub_d.h b/riscv/insns/fsub_d.h
index fcabe0e537849df5702edb1952b5c4a7c92f5134..1418a063d6ebc1a2925e0884e1faf3c94167f92d 100644 (file)
--- a/riscv/insns/fsub_d.h
+++ b/riscv/insns/fsub_d.h
@@ -1,4 +1,5 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2 ^ (uint64_t)INT64_MIN);
+WRITE_FRD(f64_sub(f64(FRS1), f64(FRS2)));
 set_fp_exceptions;