Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / fsw.h

diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h
index 23d333300e38dd60ce2e1a7bb19105fc9983b16a..8af51845f4a5306ef12cf2a703b16f15b6a0ce67 100644 (file)
--- a/riscv/insns/fsw.h
+++ b/riscv/insns/fsw.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
-mmu.store_uint32(RS1+BIMM, FRS2);
+MMU.store_uint32(RS1 + insn.s_imm(), FRS2.v[0]);