Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / lhu.h

diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h
index 1f22423b8e330ede3a84e0bc82d8b4912f137d1c..9d240702adc5c03077bf48d3ba2f5dd1d7d3161d 100644 (file)
--- a/riscv/insns/lhu.h
+++ b/riscv/insns/lhu.h
@@ -1 +1 @@
-RA = mmu.load_uint16(RB+SIMM);
+WRITE_RD(MMU.load_uint16(RS1 + insn.i_imm()));