Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / lr_w.h

diff --git a/riscv/insns/lr_w.h b/riscv/insns/lr_w.h
index 3ac474647ac5f7f0b97d9bb9f84346c0138dbd88..767251f9e07775dfe2edc01b726f1f661e43feb5 100644 (file)
--- a/riscv/insns/lr_w.h
+++ b/riscv/insns/lr_w.h
@@ -1 +1,3 @@
-RD = mmu.load_reserved_int32(RS1);
+require_extension('A');
+p->get_state()->load_reservation = RS1;
+WRITE_RD(MMU.load_int32(RS1));