Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / lw.h

diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h
index 769c9fd9306c324eee0e2959b788423def816569..4e8ed040d19e2e2a646c1ea4e97abe113a998720 100644 (file)
--- a/riscv/insns/lw.h
+++ b/riscv/insns/lw.h
@@ -1 +1 @@
-RD = mmu.load_int32(RS1+SIMM);
+WRITE_RD(MMU.load_int32(RS1 + insn.i_imm()));