Update to new privileged spec

[riscv-isa-sim.git] / riscv / insns / lwu.h

diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h
index 5535baf15b9a41ad0d5c1733191a8ca11b6e66bd..dcc4d75bab8b4d0815fdb8468fd0505d4153f309 100644 (file)
--- a/riscv/insns/lwu.h
+++ b/riscv/insns/lwu.h
@@ -1,2 +1,2 @@
-require_xpr64;
+require_rv64;
 WRITE_RD(MMU.load_uint32(RS1 + insn.i_imm()));