Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / lwu.h

diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h
index f8f98414f58aa6132f61ea32202fce8176a28994..dcc4d75bab8b4d0815fdb8468fd0505d4153f309 100644 (file)
--- a/riscv/insns/lwu.h
+++ b/riscv/insns/lwu.h
@@ -1,2 +1,2 @@
-require_xpr64;
-RD = mmu.load_uint32(RS1+SIMM);
+require_rv64;
+WRITE_RD(MMU.load_uint32(RS1 + insn.i_imm()));