Instructions are no longer member functions

[riscv-isa-sim.git] / riscv / insns / mfpcr.h

diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index d9bfc223f20d1a0de02c02d3ac7b559dde8f94d8..0f23426e508c3c8680ba93a33b925aa4270ffdd0 100644 (file)
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -1,39 +1,2 @@
 require_supervisor;
-
-reg_t val;
-
-switch(insn.rtype.rb)
-{
-  case 0:
-    val = sr;
-    break;
-  case 1:
-    val = epc;
-    break;
-  case 2:
-    val = badvaddr;
-    break;
-  case 3:
-    val = ebase;
-    break;
-
-  case 8:
-    val = MEMSIZE >> 12;
-    break;
-
-  case 17:
-    val = sim->get_fromhost();
-    break;
-
-  case 24:
-    val = pcr_k0;
-    break;
-  case 25:
-    val = pcr_k1;
-    break;
-
-  default:
-    val = -1;
-}
-
-RC = gprlen == 64 ? val : sext32(val);
+RD = p->get_pcr(insn.rtype.rs1);