Changed supervisor mode

[riscv-isa-sim.git] / riscv / insns / mfpcr.h

diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index 853842ecccd1a0c1e653270627ae8bbf11a39901..c6866699c701addd80cf9462091eb5c941ebdde6 100644 (file)
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -2,7 +2,7 @@ require_supervisor;
 
 reg_t val;
 
-switch(insn.rtype.rb)
+switch(insn.rtype.rs2)
 {
   case 0:
     val = sr;
@@ -14,19 +14,42 @@ switch(insn.rtype.rb)
     val = badvaddr;
     break;
   case 3:
-    val = ebase;
+    val = evec;
+    break;
+  case 4:
+    val = count;
+    break;
+  case 5:
+    val = compare;
+    break;
+  case 6:
+    val = cause;
+    break;
+  case 7:
+    val = mmu.get_ptbr();
     break;
 
-  case 8:
-    val = MEMSIZE >> 12;
+  case 10:
+    val = id;
+    break;
+
+  case 12:
+    val = pcr_k0;
+    break;
+  case 13:
+    val = pcr_k1;
     break;
 
   case 17:
-    val = sim->get_fromhost();
+    val = sim.get_fromhost();
+    break;
+
+  case 18:
+    val = vecbanks;
     break;
 
   default:
     val = -1;
 }
 
-RA = gprlen == 64 ? val : sext32(val);
+RD = sext_xprlen(val);