Changed supervisor mode

[riscv-isa-sim.git] / riscv / insns / mtpcr.h

diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h
index 79e28bf4c5c44a36f6bd7a86abef0c523b844657..f06fcf30ebcf117b561a0da5c1d57c06f9f474eb 100644 (file)
--- a/riscv/insns/mtpcr.h
+++ b/riscv/insns/mtpcr.h
@@ -1,33 +1,47 @@
 require_supervisor;
 
-switch(insn.rtype.rb)
+switch(insn.rtype.rs2)
 {
   case 0:
-    set_sr(RA);
+    set_sr(RS1);
     break;
   case 1:
-    epc = RA;
+    epc = RS1;
     break;
   case 3:
-    ebase = RA & ~0xFFF;
+    evec = RS1;
     break;
   case 4:
-    count = RA;
+    count = RS1;
     break;
   case 5:
     interrupts_pending &= ~(1 << TIMER_IRQ);
-    compare = RA;
+    compare = RS1;
+    break;
+  case 7:
+    mmu.set_ptbr(RS1);
     break;
 
-  case 16:
-    tohost = RA;
-    sim->set_tohost(RA);
+  case 8:
+    sim.send_ipi(RS1);
+    break;
+  case 9:
+    interrupts_pending &= ~(1 << IPI_IRQ);
+    break;
+
+  case 12:
+    pcr_k0 = RS1;
+    break;
+  case 13:
+    pcr_k1 = RS1;
     break;
 
-  case 24:
-    pcr_k0 = RA;
+  case 16:
+    sim.set_tohost(RS1);
     break;
-  case 25:
-    pcr_k1 = RA;
+
+  case 18:
+    vecbanks = RS1 & 0xff;
+    vecbanks_count = __builtin_popcountll(vecbanks);
     break;
 }