Changed supervisor mode

[riscv-isa-sim.git] / riscv / insns / mtpcr.h

diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h
index bcc613a52f27264f4ce7323252789ad71edd27d0..f06fcf30ebcf117b561a0da5c1d57c06f9f474eb 100644 (file)
--- a/riscv/insns/mtpcr.h
+++ b/riscv/insns/mtpcr.h
@@ -9,7 +9,7 @@ switch(insn.rtype.rs2)
     epc = RS1;
     break;
   case 3:
-    ebase = RS1 & ~0xFFF;
+    evec = RS1;
     break;
   case 4:
     count = RS1;
@@ -18,16 +18,30 @@ switch(insn.rtype.rs2)
     interrupts_pending &= ~(1 << TIMER_IRQ);
     compare = RS1;
     break;
+  case 7:
+    mmu.set_ptbr(RS1);
+    break;
 
-  case 16:
-    tohost = RS1;
-    sim->set_tohost(RS1);
+  case 8:
+    sim.send_ipi(RS1);
+    break;
+  case 9:
+    interrupts_pending &= ~(1 << IPI_IRQ);
     break;
 
-  case 24:
+  case 12:
     pcr_k0 = RS1;
     break;
-  case 25:
+  case 13:
     pcr_k1 = RS1;
     break;
+
+  case 16:
+    sim.set_tohost(RS1);
+    break;
+
+  case 18:
+    vecbanks = RS1 & 0xff;
+    vecbanks_count = __builtin_popcountll(vecbanks);
+    break;
 }