Update to new privileged spec

[riscv-isa-sim.git] / riscv / insns / mulw.h

diff --git a/riscv/insns/mulw.h b/riscv/insns/mulw.h
index 9f74fcfd57f8e9848f96c8067484dee7f91580a6..184dd4126081a42802619258b413031aefa68ba5 100644 (file)
--- a/riscv/insns/mulw.h
+++ b/riscv/insns/mulw.h
@@ -1,2 +1,2 @@
-require_xpr64;
+require_rv64;
 WRITE_RD(sext32(RS1 * RS2));