[sim,xcc] Changed instruction format to RISC-V

[riscv-isa-sim.git] / riscv / insns / nor.h

diff --git a/riscv/insns/nor.h b/riscv/insns/nor.h
index 1e8fa52c01a7f752a644227509673b2e3b4531df..5bb7e897f02332f3aad0ab60eef0be773867fd66 100644 (file)
--- a/riscv/insns/nor.h
+++ b/riscv/insns/nor.h
@@ -1 +1 @@
-RD = ~(RS | RT);
+RC = ~(RA | RB);