WIP. Doesn't work.
[riscv-isa-sim.git] / riscv / insns / or.h
index d88c9f84e7c2c97856ec83b4f436af12c7d85920..3f2fffc22e2a2ca0ae6663c79f31d27f5cf94ffb 100644 (file)
@@ -1 +1 @@
-RC = RA | RB;
+WRITE_RD(RS1 | RS2);