[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / remuw.h

diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h
index d028488e9d059cc7baa0ee81b97223cf39ac19a9..26decf20f286829ff1b1a8895f74dc3a442a1daa 100644 (file)
--- a/riscv/insns/remuw.h
+++ b/riscv/insns/remuw.h
@@ -1,2 +1,2 @@
-RC = sext32(uint32_t(RA) % uint32_t(RB));
+RDR = sext32(uint32_t(RS1) % uint32_t(RS2));