[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / remuw.h

diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h
index 26decf20f286829ff1b1a8895f74dc3a442a1daa..8234af382726a3ae1523de563637902e586d212f 100644 (file)
--- a/riscv/insns/remuw.h
+++ b/riscv/insns/remuw.h
@@ -1,2 +1,5 @@
-RDR = sext32(uint32_t(RS1) % uint32_t(RS2));
-
+require_xpr64;
+if(RS2 == 0)
+  RD = RS1;
+else
+  RD = sext32(zext_xprlen(RS1) % zext_xprlen(RS2));