[sim,xcc] Changed instruction format to RISC-V

[riscv-isa-sim.git] / riscv / insns / sb.h

diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h
index f70b2eff213c860a78d20a8b0c6ea53b7e6f1918..618140d3b03fca8c619809ba6fd41b3c78f01974 100644 (file)
--- a/riscv/insns/sb.h
+++ b/riscv/insns/sb.h
@@ -1 +1 @@
-mmu.store_uint8(RS+SIMM, RT);
+mmu.store_uint8(RB+SIMM, RA);