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Fix implementation of FMIN/FMAX NaN case
[riscv-isa-sim.git]
/
riscv
/
insns
/
sb.h
diff --git
a/riscv/insns/sb.h
b/riscv/insns/sb.h
index af5bd10240fb63d249915809bb9930b62b0fbf0a..8729c2d47f46f5884e4d88ea4cb95e2e0a49c54f 100644
(file)
--- a/
riscv/insns/sb.h
+++ b/
riscv/insns/sb.h
@@
-1
+1
@@
-
mmu.store_uint8(RS1+BIMM
, RS2);
+
MMU.store_uint8(RS1 + insn.s_imm()
, RS2);