[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / sh.h

diff --git a/riscv/insns/sh.h b/riscv/insns/sh.h
index e0fdc0a4070fa5a65d38de769c41a8ad437523a4..bbc2bda3f8ca59f6e0bf544ea20a2a5984fce318 100644 (file)
--- a/riscv/insns/sh.h
+++ b/riscv/insns/sh.h
@@ -1 +1 @@
-mmu.store_uint16(RB+SIMM, RA);
+mmu.store_uint16(RS1+SIMM, RS2);