[sim] fixed bug in which shift operands were reversed

[riscv-isa-sim.git] / riscv / insns / sll.h

diff --git a/riscv/insns/sll.h b/riscv/insns/sll.h
index fe32e895f1e81fdb01142b82555eaf55c5a6ecb2..8b6bc700f0bbbcfd76a6b58607d7ba799c4c6889 100644 (file)
--- a/riscv/insns/sll.h
+++ b/riscv/insns/sll.h
@@ -1 +1,2 @@
-RD = sext32(RT << SHAMT);
+require64;
+RDR = RS1 << (RS2 & 0x3F);