Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / slli.h

diff --git a/riscv/insns/slli.h b/riscv/insns/slli.h
index 151d97023f8be409106d7679606ec87efbd9eb5b..ff9c8c39bf9d6d3521c11e55bdcd240d1f8e98ad 100644 (file)
--- a/riscv/insns/slli.h
+++ b/riscv/insns/slli.h
@@ -1,8 +1,8 @@
 if(xpr64)
-  RD = RS1 << SHAMT;
+  WRITE_RD(RS1 << SHAMT);
 else
 {
   if(SHAMT & 0x20)
     throw trap_illegal_instruction();
-  RD = sext32(RS1 << SHAMT);
+  WRITE_RD(sext32(RS1 << SHAMT));
 }