Update to new privileged spec

[riscv-isa-sim.git] / riscv / insns / sllw.h

diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h
index 25e717af502038056ab50919f13107bc9f70cef7..affe894441be2778b253a7f2ef33e764fd759468 100644 (file)
--- a/riscv/insns/sllw.h
+++ b/riscv/insns/sllw.h
@@ -1,2 +1,2 @@
-require_xpr64;
+require_rv64;
 WRITE_RD(sext32(RS1 << (RS2 & 0x1F)));