Update to new privileged spec

[riscv-isa-sim.git] / riscv / insns / sllw.h

diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h
index f694a2ff3ce019a24881f8d528c200f08107ecfe..affe894441be2778b253a7f2ef33e764fd759468 100644 (file)
--- a/riscv/insns/sllw.h
+++ b/riscv/insns/sllw.h
@@ -1 +1,2 @@
-RC = sext32(RB << (RA & 0x1F));
+require_rv64;
+WRITE_RD(sext32(RS1 << (RS2 & 0x1F)));