WIP. Doesn't work.
[riscv-isa-sim.git] / riscv / insns / sltiu.h
index 3b6390f5d7acfb92eab8b7319724c86cb90cbe7e..f39845713fbc80eda8acbb8ed83cb6a68b0b7f09 100644 (file)
@@ -1 +1 @@
-RT = cmp_trunc(RS) < cmp_trunc(SIMM);
+WRITE_RD(RS1 < reg_t(insn.i_imm()));