WIP. Doesn't work.
[riscv-isa-sim.git] / riscv / insns / sltiu.h
index b7c8ce64f10cd1c9e3bfb3c6242a8d56f66ce1aa..f39845713fbc80eda8acbb8ed83cb6a68b0b7f09 100644 (file)
@@ -1 +1 @@
-RDI = cmp_trunc(RS1) < cmp_trunc(SIMM);
+WRITE_RD(RS1 < reg_t(insn.i_imm()));