[opcodes] generate latex and verilog correctly

[riscv-isa-sim.git] / riscv / insns / sqrt_d_rm.h

diff --git a/riscv/insns/sqrt_d_rm.h b/riscv/insns/sqrt_d_rm.h
index 5e93b27640a0d91ea1e572914a608c1a1ea75a4b..7647c9c8d630f0dcf2b075998e3c881cbe241c28 100644 (file)
--- a/riscv/insns/sqrt_d_rm.h
+++ b/riscv/insns/sqrt_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_sqrt(FRS1);
+FRD = f64_sqrt(FRS1);
 set_fp_exceptions;