Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / sra.h

diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h
index c2decb99b2e64148540c9a12c17f6021b433721c..403b9b733a5e3cce36c7885e906a80f4dace1309 100644 (file)
--- a/riscv/insns/sra.h
+++ b/riscv/insns/sra.h
@@ -1 +1 @@
-RC = sext32(sreg_t(RB) >> SHAMT);
+WRITE_RD(sext_xlen(sext_xlen(RS1) >> (RS2 & (xlen-1))));