Update to new privileged ISA

[riscv-isa-sim.git] / riscv / insns / sret.h

diff --git a/riscv/insns/sret.h b/riscv/insns/sret.h
new file mode 100644 (file)
index 0000000..442b00b
--- /dev/null
+++ b/riscv/insns/sret.h
@@ -0,0 +1,5 @@
+require_supervisor;
+p->set_pcr(CSR_STATUS, ((p->get_state()->sr & ~(SR_S | SR_EI)) |
+                       ((p->get_state()->sr & SR_PS) ? SR_S : 0)) |
+                       ((p->get_state()->sr & SR_PEI) ? SR_EI : 0));
+set_pc(p->get_state()->epc);