[opcodes] generate latex and verilog correctly

[riscv-isa-sim.git] / riscv / insns / srl.h

diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h
index fa17eb71eccae0159712beb743a81689eb2ff77d..87138dab4f2ee591a18054008a9a5e509f5108b9 100644 (file)
--- a/riscv/insns/srl.h
+++ b/riscv/insns/srl.h
@@ -1,2 +1,2 @@
 require64;
-RDR = RS1 >> (RS2 & 0x3F);
+RD = RS1 >> (RS2 & 0x3F);