Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / sub.h

diff --git a/riscv/insns/sub.h b/riscv/insns/sub.h
index 2b1e0570ad4213cce46ce84a1e78adf849ff7597..95fb83e3340f71beb2ca64115ed14bda85f29ec4 100644 (file)
--- a/riscv/insns/sub.h
+++ b/riscv/insns/sub.h
@@ -1 +1 @@
-RD = sext_xprlen(RS1 - RS2);
+WRITE_RD(sext_xprlen(RS1 - RS2));