[sim] add vt stuff

[riscv-isa-sim.git] / riscv / insns / sw_v.h

diff --git a/riscv/insns/sw_v.h b/riscv/insns/sw_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..276da954f7a8f2258e33857c1cf1f8530bd2c7f2 100644 (file)
--- a/riscv/insns/sw_v.h
+++ b/riscv/insns/sw_v.h
@@ -0,0 +1 @@
+VEC_STORE(RD, store_uint32, 4);