Fix page table walker not respecting valid bit

[riscv-isa-sim.git] / riscv / mmu.cc

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 602b09010399899a79c2db74248d310a5fe51e8b..4b7166f44bb5038a8f17a51f9486400bed7adf8a 100644 (file)
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -153,7 +153,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode)
       base = ppn << PGSHIFT;
     } else if ((pte & PTE_U) ? supervisor && pum : !supervisor) {
       break;
-    } else if (!(pte & PTE_R) && (pte & PTE_W)) { // reserved
+    } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) {
       break;
     } else if (type == FETCH ? !(pte & PTE_X) :
                type == LOAD ?  !(pte & PTE_R) && !(mxr && (pte & PTE_X)) :