Improve performance for branchy code

[riscv-isa-sim.git] / riscv / mmu.cc

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index b2c8c9864082689954a4ca25dc28e736a934e1e8..4675f75f61734963054980c6c2c8efa448ff289b 100644 (file)
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -1,10 +1,11 @@
+// See LICENSE for license details.
+
 #include "mmu.h"
 #include "sim.h"
 #include "processor.h"
 
 mmu_t::mmu_t(char* _mem, size_t _memsz)
- : mem(_mem), memsz(_memsz), badvaddr(0),
-   ptbr(0), supervisor(true), vm_enabled(false)
+ : mem(_mem), memsz(_memsz), proc(NULL)
 {
   flush_tlb();
 }
@@ -13,6 +14,12 @@ mmu_t::~mmu_t()
 {
 }
 
+void mmu_t::flush_icache()
+{
+  for (size_t i = 0; i < ICACHE_SIZE; i++)
+    icache[i].tag = -1;
+}
+
 void mmu_t::flush_tlb()
 {
   memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag));
@@ -22,52 +29,62 @@ void mmu_t::flush_tlb()
   flush_icache();
 }
 
-void mmu_t::flush_icache()
-{
-  memset(icache_tag, -1, sizeof(icache_tag));
-}
-
-void* mmu_t::refill(reg_t addr, bool store, bool fetch)
+void* mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch)
 {
   reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
-  reg_t expected_tag = addr & ~(PGSIZE-1);
+  reg_t expected_tag = addr >> PGSHIFT;
 
   reg_t pte = walk(addr);
 
   reg_t pte_perm = pte & PTE_PERM;
-  if(supervisor) // shift supervisor permission bits into user perm bits
+  if (proc == NULL || (proc->state.sr & SR_S))
     pte_perm = (pte_perm/(PTE_SX/PTE_UX)) & PTE_PERM;
-  pte_perm |= pte & PTE_E;
+  pte_perm |= pte & PTE_V;
 
-  reg_t perm = (fetch ? PTE_UX : store ? PTE_UW : PTE_UR) | PTE_E;
+  reg_t perm = (fetch ? PTE_UX : store ? PTE_UW : PTE_UR) | PTE_V;
   if(unlikely((pte_perm & perm) != perm))
   {
-    badvaddr = addr;
-    throw store ? trap_store_access_fault
-        : fetch ? trap_instruction_access_fault
-        :         trap_load_access_fault;
+    if (fetch)
+      throw trap_instruction_access_fault();
+
+    if (store)
+      throw trap_store_access_fault(addr);
+    throw trap_load_access_fault(addr);
   }
 
-  tlb_load_tag[idx] = (pte_perm & PTE_UR) ? expected_tag : -1;
-  tlb_store_tag[idx] = (pte_perm & PTE_UW) ? expected_tag : -1;
-  tlb_insn_tag[idx] = (pte_perm & PTE_UX) ? expected_tag : -1;
-  tlb_data[idx] = (long)(pte >> PTE_PPN_SHIFT << PGSHIFT) + (long)mem;
+  reg_t pgoff = addr & (PGSIZE-1);
+  reg_t pgbase = pte >> PGSHIFT << PGSHIFT;
+  reg_t paddr = pgbase + pgoff;
+
+  if (unlikely(tracer.interested_in_range(pgbase, pgbase + PGSIZE, store, fetch)))
+    tracer.trace(paddr, bytes, store, fetch);
+  else
+  {
+    tlb_load_tag[idx] = (pte_perm & PTE_UR) ? expected_tag : -1;
+    tlb_store_tag[idx] = (pte_perm & PTE_UW) ? expected_tag : -1;
+    tlb_insn_tag[idx] = (pte_perm & PTE_UX) ? expected_tag : -1;
+    tlb_data[idx] = mem + pgbase - (addr & ~(PGSIZE-1));
+  }
 
-  return (void*)(((long)addr & (PGSIZE-1)) | tlb_data[idx]);
+  return mem + paddr;
 }
 
 pte_t mmu_t::walk(reg_t addr)
 {
   pte_t pte = 0;
 
-  if(!vm_enabled)
+  // the address must be a canonical sign-extended VA_BITS-bit number
+  int shift = 8*sizeof(reg_t) - VA_BITS;
+  if (((sreg_t)addr << shift >> shift) != (sreg_t)addr)
+    ;
+  else if (proc == NULL || !(proc->state.sr & SR_VM))
   {
     if(addr < memsz)
-      pte = PTE_E | PTE_PERM | ((addr >> PGSHIFT) << PTE_PPN_SHIFT);
+      pte = PTE_V | PTE_PERM | ((addr >> PGSHIFT) << PGSHIFT);
   }
   else
   {
-    reg_t base = ptbr;
+    reg_t base = proc->get_state()->ptbr;
     reg_t ptd;
 
     int ptshift = (LEVELS-1)*PTIDXBITS;
@@ -80,25 +97,31 @@ pte_t mmu_t::walk(reg_t addr)
         break;
 
       ptd = *(pte_t*)(mem+pte_addr);
-      if(ptd & PTE_E)
+
+      if (!(ptd & PTE_V)) // invalid mapping
+        break;
+      else if (ptd & PTE_T) // next level of page table
+        base = (ptd >> PGSHIFT) << PGSHIFT;
+      else // the actual PTE
       {
         // if this PTE is from a larger PT, fake a leaf
         // PTE so the TLB will work right
         reg_t vpn = addr >> PGSHIFT;
-        ptd |= (vpn & ((1<<(ptshift))-1)) << PTE_PPN_SHIFT;
+        ptd |= (vpn & ((1<<(ptshift))-1)) << PGSHIFT;
 
-        // fault if physical addr is invalid
-        reg_t ppn = ptd >> PTE_PPN_SHIFT;
-        if((ppn << PGSHIFT) + (addr & (PGSIZE-1)) < memsz)
+        // fault if physical addr is out of range
+        if (((ptd >> PGSHIFT) << PGSHIFT) < memsz)
           pte = ptd;
         break;
       }
-      else if(!(ptd & PTE_T))
-        break;
-
-      base = (ptd >> PTE_PPN_SHIFT) << PGSHIFT;
     }
   }
 
   return pte;
 }
+
+void mmu_t::register_memtracer(memtracer_t* t)
+{
+  flush_tlb();
+  tracer.hook(t);
+}