#include "sim.h"
#include "processor.h"
-mmu_t::mmu_t(char* _mem, size_t _memsz)
- : mem(_mem), memsz(_memsz), badvaddr(0),
- ptbr(0), proc(NULL)
+mmu_t::mmu_t(sim_t* sim, processor_t* proc)
+ : sim(sim), proc(proc)
{
flush_tlb();
}
void mmu_t::flush_icache()
{
- memset(icache_tag, -1, sizeof(icache_tag));
+ for (size_t i = 0; i < ICACHE_ENTRIES; i++)
+ icache[i].tag = -1;
}
void mmu_t::flush_tlb()
memset(tlb_store_tag, -1, sizeof(tlb_store_tag));
flush_icache();
- yield_load_reservation();
}
-reg_t mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch)
+reg_t mmu_t::translate(reg_t addr, access_type type)
{
- reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
- reg_t expected_tag = addr & ~(PGSIZE-1);
+ if (!proc)
+ return addr;
- reg_t pte = walk(addr);
+ reg_t mode = proc->state.prv;
+ if (type != FETCH) {
+ if (!proc->state.dcsr.cause && get_field(proc->state.mstatus, MSTATUS_MPRV))
+ mode = get_field(proc->state.mstatus, MSTATUS_MPP);
+ }
+ if (get_field(proc->state.mstatus, MSTATUS_VM) == VM_MBARE)
+ mode = PRV_M;
- reg_t pte_perm = pte & PTE_PERM;
- if (proc == NULL || (proc->sr & SR_S))
- pte_perm = (pte_perm/(PTE_SX/PTE_UX)) & PTE_PERM;
- pte_perm |= pte & PTE_V;
+ if (mode == PRV_M) {
+ reg_t msb_mask = (reg_t(2) << (proc->xlen-1))-1; // zero-extend from xlen
+ return addr & msb_mask;
+ }
+ return walk(addr, type, mode) | (addr & (PGSIZE-1));
+}
- reg_t perm = (fetch ? PTE_UX : store ? PTE_UW : PTE_UR) | PTE_V;
- if(unlikely((pte_perm & perm) != perm))
- {
- if (fetch)
- throw trap_instruction_access_fault;
+const uint16_t* mmu_t::fetch_slow_path(reg_t vaddr)
+{
+ reg_t paddr = translate(vaddr, FETCH);
- badvaddr = addr;
- throw store ? trap_store_access_fault : trap_load_access_fault;
+ // mmu_t::walk() returns -1 if it can't find a match. Of course -1 could also
+ // be a valid address.
+ if (paddr == ~(reg_t) 0 && vaddr != ~(reg_t) 0) {
+ throw trap_instruction_access_fault(vaddr);
}
- reg_t pgoff = addr & (PGSIZE-1);
- reg_t pgbase = pte >> PGSHIFT << PGSHIFT;
- reg_t paddr = pgbase + pgoff;
+ if (sim->addr_is_mem(paddr)) {
+ refill_tlb(vaddr, paddr, FETCH);
+ return (const uint16_t*)sim->addr_to_mem(paddr);
+ } else {
+ if (!sim->mmio_load(paddr, sizeof fetch_temp, (uint8_t*)&fetch_temp))
+ throw trap_instruction_access_fault(vaddr);
+ return &fetch_temp;
+ }
+}
- if (unlikely(tracer.interested_in_range(pgbase, pgbase + PGSIZE, store, fetch)))
- tracer.trace(paddr, bytes, store, fetch);
- else
- {
- tlb_load_tag[idx] = (pte_perm & PTE_UR) ? expected_tag : -1;
- tlb_store_tag[idx] = (pte_perm & PTE_UW) ? expected_tag : -1;
- tlb_insn_tag[idx] = (pte_perm & PTE_UX) ? expected_tag : -1;
- tlb_data[idx] = pgbase;
+void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes)
+{
+ reg_t paddr = translate(addr, LOAD);
+ if (sim->addr_is_mem(paddr)) {
+ memcpy(bytes, sim->addr_to_mem(paddr), len);
+ if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
+ tracer.trace(paddr, len, LOAD);
+ else
+ refill_tlb(addr, paddr, LOAD);
+ } else if (!sim->mmio_load(paddr, len, bytes)) {
+ throw trap_load_access_fault(addr);
}
+}
- return paddr;
+void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes)
+{
+ reg_t paddr = translate(addr, STORE);
+ if (sim->addr_is_mem(paddr)) {
+ memcpy(sim->addr_to_mem(paddr), bytes, len);
+ if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
+ tracer.trace(paddr, len, STORE);
+ else
+ refill_tlb(addr, paddr, STORE);
+ } else if (!sim->mmio_store(paddr, len, bytes)) {
+ throw trap_store_access_fault(addr);
+ }
}
-pte_t mmu_t::walk(reg_t addr)
+void mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, access_type type)
{
- pte_t pte = 0;
+ reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES;
+ reg_t expected_tag = vaddr >> PGSHIFT;
+
+ if (tlb_load_tag[idx] != expected_tag) tlb_load_tag[idx] = -1;
+ if (tlb_store_tag[idx] != expected_tag) tlb_store_tag[idx] = -1;
+ if (tlb_insn_tag[idx] != expected_tag) tlb_insn_tag[idx] = -1;
- // the address must be a canonical sign-extended VA_BITS-bit number
- int shift = 8*sizeof(reg_t) - VA_BITS;
- if (((sreg_t)addr << shift >> shift) != (sreg_t)addr)
- ;
- else if (proc == NULL || !(proc->sr & SR_VM))
+ if (type == FETCH) tlb_insn_tag[idx] = expected_tag;
+ else if (type == STORE) tlb_store_tag[idx] = expected_tag;
+ else tlb_load_tag[idx] = expected_tag;
+
+ tlb_data[idx] = sim->addr_to_mem(paddr) - vaddr;
+}
+
+reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode)
+{
+ int levels, ptidxbits, ptesize;
+ switch (get_field(proc->get_state()->mstatus, MSTATUS_VM))
{
- if(addr < memsz)
- pte = PTE_V | PTE_PERM | ((addr >> PGSHIFT) << PGSHIFT);
+ case VM_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break;
+ case VM_SV39: levels = 3; ptidxbits = 9; ptesize = 8; break;
+ case VM_SV48: levels = 4; ptidxbits = 9; ptesize = 8; break;
+ default: abort();
}
- else
- {
- reg_t base = ptbr;
- reg_t ptd;
-
- int ptshift = (LEVELS-1)*PTIDXBITS;
- for(reg_t i = 0; i < LEVELS; i++, ptshift -= PTIDXBITS)
- {
- reg_t idx = (addr >> (PGSHIFT+ptshift)) & ((1<<PTIDXBITS)-1);
-
- reg_t pte_addr = base + idx*sizeof(pte_t);
- if(pte_addr >= memsz)
- break;
-
- ptd = *(pte_t*)(mem+pte_addr);
-
- if (!(ptd & PTE_V)) // invalid mapping
- break;
- else if (ptd & PTE_T) // next level of page table
- base = (ptd >> PGSHIFT) << PGSHIFT;
- else // the actual PTE
- {
- // if this PTE is from a larger PT, fake a leaf
- // PTE so the TLB will work right
- reg_t vpn = addr >> PGSHIFT;
- ptd |= (vpn & ((1<<(ptshift))-1)) << PGSHIFT;
-
- // fault if physical addr is out of range
- if (((ptd >> PGSHIFT) << PGSHIFT) < memsz)
- pte = ptd;
- break;
- }
+
+ bool supervisor = mode == PRV_S;
+ bool pum = get_field(proc->state.mstatus, MSTATUS_PUM);
+ bool mxr = get_field(proc->state.mstatus, MSTATUS_MXR);
+
+ // verify bits xlen-1:va_bits-1 are all equal
+ int va_bits = PGSHIFT + levels * ptidxbits;
+ reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1;
+ reg_t masked_msbs = (addr >> (va_bits-1)) & mask;
+ if (masked_msbs != 0 && masked_msbs != mask)
+ return -1;
+
+ reg_t base = proc->get_state()->sptbr << PGSHIFT;
+ int ptshift = (levels - 1) * ptidxbits;
+ for (int i = 0; i < levels; i++, ptshift -= ptidxbits) {
+ reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
+
+ // check that physical address of PTE is legal
+ reg_t pte_addr = base + idx * ptesize;
+ if (!sim->addr_is_mem(pte_addr))
+ break;
+
+ void* ppte = sim->addr_to_mem(pte_addr);
+ reg_t pte = ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
+ reg_t ppn = pte >> PTE_PPN_SHIFT;
+
+ if (PTE_TABLE(pte)) { // next level of page table
+ base = ppn << PGSHIFT;
+ } else if ((pte & PTE_U) ? supervisor && pum : !supervisor) {
+ break;
+ } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) {
+ break;
+ } else if (type == FETCH ? !(pte & PTE_X) :
+ type == LOAD ? !(pte & PTE_R) && !(mxr && (pte & PTE_X)) :
+ !((pte & PTE_R) && (pte & PTE_W))) {
+ break;
+ } else {
+ // set accessed and possibly dirty bits.
+ *(uint32_t*)ppte |= PTE_A | ((type == STORE) * PTE_D);
+ // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
+ reg_t vpn = addr >> PGSHIFT;
+ reg_t value = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
+ return value;
}
}
- return pte;
+ return -1;
}
void mmu_t::register_memtracer(memtracer_t* t)
projects / riscv-isa-sim.git / blobdiff