Ignore MPRV in Debug Mode.

[riscv-isa-sim.git] / riscv / mmu.cc

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 514547cafbacaea8f80a3554081c1f8cfb74689e..e44c027b53ab2607dfa3bda746339e51ad64248d 100644 (file)
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -37,7 +37,7 @@ reg_t mmu_t::translate(reg_t addr, access_type type)
   reg_t mode = proc->state.prv;
   bool pum = false;
   if (type != FETCH) {
-    if (get_field(proc->state.mstatus, MSTATUS_MPRV))
+    if (!proc->state.dcsr.cause && get_field(proc->state.mstatus, MSTATUS_MPRV))
       mode = get_field(proc->state.mstatus, MSTATUS_MPP);
     pum = (mode == PRV_S && get_field(proc->state.mstatus, MSTATUS_PUM));
   }
@@ -51,28 +51,6 @@ reg_t mmu_t::translate(reg_t addr, access_type type)
   return walk(addr, type, mode > PRV_U, pum) | (addr & (PGSIZE-1));
 }
 
-const char* mmu_t::fill_from_mmio(reg_t vaddr, reg_t paddr)
-{
-  reg_t rv_start = paddr & PGMASK;
-  char* spike_start = proc->sim->mmio_page(rv_start);
-
-  if (!spike_start)
-    return NULL;
-
-  // TODO: refactor with refill_tlb()
-  reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES;
-  reg_t expected_tag = vaddr >> PGSHIFT;
-
-  if (tlb_load_tag[idx] != expected_tag) tlb_load_tag[idx] = -1;
-  if (tlb_store_tag[idx] != expected_tag) tlb_store_tag[idx] = -1;
-  if (tlb_insn_tag[idx] != expected_tag) tlb_insn_tag[idx] = -1;
-
-  tlb_insn_tag[idx] = expected_tag;
-  tlb_data[idx] = spike_start - DEBUG_START;
-
-  return spike_start + (paddr & ~PGMASK);
-}
-
 const uint16_t* mmu_t::fetch_slow_path(reg_t vaddr)
 {
   reg_t paddr = translate(vaddr, FETCH);
@@ -139,6 +117,7 @@ void mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, access_type type)
 
 reg_t mmu_t::walk(reg_t addr, access_type type, bool supervisor, bool pum)
 {
+  fprintf(stderr, "walk 0x%lx\n", addr);
   int levels, ptidxbits, ptesize;
   switch (get_field(proc->get_state()->mstatus, MSTATUS_VM))
   {
@@ -152,6 +131,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, bool supervisor, bool pum)
   int va_bits = PGSHIFT + levels * ptidxbits;
   reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1;
   reg_t masked_msbs = (addr >> (va_bits-1)) & mask;
+  fprintf(stderr, "walk masked_msbs=0x%lx, mask=0x%lx\n", masked_msbs, mask);
   if (masked_msbs != 0 && masked_msbs != mask)
     return -1;
 
@@ -162,6 +142,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, bool supervisor, bool pum)
 
     // check that physical address of PTE is legal
     reg_t pte_addr = base + idx * ptesize;
+    fprintf(stderr, "pte_addr=0x%lx\n", pte_addr);
     if (!sim->addr_is_mem(pte_addr))
       break;
 
@@ -169,18 +150,25 @@ reg_t mmu_t::walk(reg_t addr, access_type type, bool supervisor, bool pum)
     reg_t pte = ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
     reg_t ppn = pte >> PTE_PPN_SHIFT;
 
+    fprintf(stderr, "pte=0x%lx\n", pte);
+
     if (PTE_TABLE(pte)) { // next level of page table
       base = ppn << PGSHIFT;
     } else if (pum && PTE_CHECK_PERM(pte, 0, type == STORE, type == FETCH)) {
+      fprintf(stderr, "pum fail\n");
       break;
     } else if (!PTE_CHECK_PERM(pte, supervisor, type == STORE, type == FETCH)) {
+      fprintf(stderr, "perm(0x%lx, %d, %d, %d)\n",
+          pte, supervisor, type==STORE, type==FETCH);
       break;
     } else {
       // set referenced and possibly dirty bits.
       *(uint32_t*)ppte |= PTE_R | ((type == STORE) * PTE_D);
       // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
       reg_t vpn = addr >> PGSHIFT;
-      return (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
+      reg_t value = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
+      fprintf(stderr, "  -> 0x%lx\n", value);
+      return value;
     }
   }