reg_t mode = proc->state.prv;
bool pum = false;
if (type != FETCH) {
- if (get_field(proc->state.mstatus, MSTATUS_MPRV))
+ if (!proc->state.dcsr.cause && get_field(proc->state.mstatus, MSTATUS_MPRV))
mode = get_field(proc->state.mstatus, MSTATUS_MPP);
pum = (mode == PRV_S && get_field(proc->state.mstatus, MSTATUS_PUM));
}
if (get_field(proc->state.mstatus, MSTATUS_VM) == VM_MBARE)
mode = PRV_M;
- fprintf(stderr, "translate(0x%lx, %d), mstatus=0x%lx, prv=%ld, mode=%ld, pum=%d\n",
- addr, type, proc->state.mstatus, proc->state.prv, mode, pum);
if (mode == PRV_M) {
reg_t msb_mask = (reg_t(2) << (proc->xlen-1))-1; // zero-extend from xlen
return addr & msb_mask;
void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes)
{
reg_t paddr = translate(addr, LOAD);
- fprintf(stderr, "load_slow_path 0x%lx -> 0x%lx\n", addr, paddr);
if (sim->addr_is_mem(paddr)) {
memcpy(bytes, sim->addr_to_mem(paddr), len);
if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes)
{
reg_t paddr = translate(addr, STORE);
- fprintf(stderr, "store_slow_path 0x%lx -> 0x%lx\n", addr, paddr);
if (sim->addr_is_mem(paddr)) {
memcpy(sim->addr_to_mem(paddr), bytes, len);
if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
reg_t mmu_t::walk(reg_t addr, access_type type, bool supervisor, bool pum)
{
+ fprintf(stderr, "walk 0x%lx\n", addr);
int levels, ptidxbits, ptesize;
switch (get_field(proc->get_state()->mstatus, MSTATUS_VM))
{
int va_bits = PGSHIFT + levels * ptidxbits;
reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1;
reg_t masked_msbs = (addr >> (va_bits-1)) & mask;
+ fprintf(stderr, "walk masked_msbs=0x%lx, mask=0x%lx\n", masked_msbs, mask);
if (masked_msbs != 0 && masked_msbs != mask)
return -1;
// check that physical address of PTE is legal
reg_t pte_addr = base + idx * ptesize;
+ fprintf(stderr, "pte_addr=0x%lx\n", pte_addr);
if (!sim->addr_is_mem(pte_addr))
break;
reg_t pte = ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
reg_t ppn = pte >> PTE_PPN_SHIFT;
+ fprintf(stderr, "pte=0x%lx\n", pte);
+
if (PTE_TABLE(pte)) { // next level of page table
base = ppn << PGSHIFT;
} else if (pum && PTE_CHECK_PERM(pte, 0, type == STORE, type == FETCH)) {
+ fprintf(stderr, "pum fail\n");
break;
} else if (!PTE_CHECK_PERM(pte, supervisor, type == STORE, type == FETCH)) {
+ fprintf(stderr, "perm(0x%lx, %d, %d, %d)\n",
+ pte, supervisor, type==STORE, type==FETCH);
break;
} else {
// set referenced and possibly dirty bits.
*(uint32_t*)ppte |= PTE_R | ((type == STORE) * PTE_D);
// for superpage mappings, make a fake leaf PTE for the TLB's benefit.
reg_t vpn = addr >> PGSHIFT;
- return (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
+ reg_t value = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
+ fprintf(stderr, " -> 0x%lx\n", value);
+ return value;
}
}