struct icache_entry_t {
reg_t tag;
- reg_t pad;
+ struct icache_entry_t* next;
insn_fetch_t data;
};
class mmu_t
{
public:
- mmu_t(sim_t* sim, processor_t* proc);
+ mmu_t(simif_t* sim, processor_t* proc);
~mmu_t();
inline reg_t misaligned_load(reg_t addr, size_t size)
insn_fetch_t fetch = {proc->decode_insn(insn), insn};
entry->tag = addr;
+ entry->next = &icache[icache_index(addr + length)];
entry->data = fetch;
reg_t paddr = tlb_entry.target_offset + addr;;
void register_memtracer(memtracer_t*);
+ int is_dirty_enabled()
+ {
+#ifdef RISCV_ENABLE_DIRTY
+ return 1;
+#else
+ return 0;
+#endif
+ }
+
+ int is_misaligned_enabled()
+ {
+#ifdef RISCV_ENABLE_MISALIGNED
+ return 1;
+#else
+ return 0;
+#endif
+ }
+
private:
- sim_t* sim;
+ simif_t* sim;
processor_t* proc;
memtracer_list_t tracer;
uint16_t fetch_temp;